1. Field of the Invention
The present invention relates to circuits for removing duty cycle distortion jitter from a signal. In particular, the invention relates to the use of phase-lock loops and recovered clock signals to provide feedback control of the jitter.
2. Description of the Related Art
Transmitters in a communication system are not ideal. One of the nonidealities is rise/fall mismatch, which generates duty cycle distortion ("DCD") jitter.
FIG. 1a illustrates a case with no DCD, that is, rise time t.sub.r is equal to fall time t.sub.f. The signal RX.sub.data shows the possible transitions of the data signal. The signal RXC.sub.r shows a recovered clock generated from a phase-lock loop ("PLL") locked to rising edge transitions of RX.sub.data. The signal RXC.sub.f shows a recovered clock generated from a PLL locked to falling edge transitions of RX.sub.data. Note that RXC.sub.r and RXC.sub.f are exactly in phase.
FIG. 1b illustrates a case where t.sub.r is less than t.sub.f. This causes RXC.sub.r to lead RXC.sub.f by a phase differential.
FIG. 1c illustrates that when t.sub.r is greater than t.sub.f, RXC.sub.r follows RXC.sub.f by a phase differential.
Rise/fall mismatch eats into the jitter budget for the system. For example, with a typical 100Base-T ethernet, fixed jitter caused by rise/fall mismatch can account for 22% of a zero to peak jitter budget of 3 ns. As embedded clock frequencies continue to increase, rise/fall mismatch becomes an even larger portion of the jitter budget.
This problem is not limited to the receiver. It is difficult to design a transmitter that can meet the strict rise/fall mismatch specifications of 100Base-T and 1000FX/CX ethernet. If a method for removing this duty cycle distortion ("DCD") prior to clock recovery could be developed, the clock recovery system would have an easier task because it would be dealing with reduced jitter on the input signal.
For example, in 100Base-T ethernet, a signal with 0.67 ns DCD, 1 ns data-dependent jitter ("DDJ"), and 1.3 ns Gaussian jitter ("RJ") has an eye of only 1 ns zero to peak. If the DCD could be eliminated, the eye increases to 1.67 ns zero to peak, a 67% increase. This improvement could be used to design a cheaper clock recovery module. It could also be used to design a cheaper DDJ equalizer, which removes most of the DDJ and consumes most of the power and chip area in a 100Base-T physical layer.
A PLL phase detector can be made more robust to DCD by looking at both edges of data. This will allow the PLL to lock to the midpoint of both means in a bimodal jitter distribution. Because the PLL gives equal weight to rising and falling edge phase errors, the PLL locks to halfway between where a PLL looking at only rising edges and a PLL looking at only falling edges would lock to. This means that the eye is reduced by an amount equal to half the DCD. This is the best a clock recovery PLL can do without DCD equalization.
In addition, some present methods of DCD equalization sample the rise and fall times and then compute an adjustment after a defined number of samples have been collected. There is a need for adjustment computed in a more stable manner.
Furthermore, some present methods only look at phase errors when the NRZ bit sequence is `0101` or `1010`, that is, they require two transitions separated by one bit. This wastes some of the phase information. There is a need to examine all transitions to take advantage of more phase information.
Finally, some present methods correct DCD where the adjust resolution is a buffer delay. There is a need for decreasing this adjust resolution.